/*
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
 * Copyright 2016-2021 NXP
 * All rights reserved.
 *
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
#ifndef _APP_H_
#define _APP_H_

/*******************************************************************************
 * Definitions
 ******************************************************************************/
/*${macro:start}*/
#define NAND_EXAMPLE_FLEXSPI                 FLEXSPI
#define NAND_FLASH_SIZE                      0x2000 /* 64Mb/KByte */
#define NAND_EXAMPLE_FLEXSPI_AMBA_BASE       FlexSPI_AMBA_BASE
#define NAND_FLASH_PAGE_SIZE                 2048
#define NAND_EXAMPLE_SECTOR                  0
#define NAND_SECTOR_SIZE                     0x1000 /* 4K */
#define NAND_EXAMPLE_FLEXSPI_CLOCK           kCLOCK_FlexSpi
#define NAND_FLASH_PORT                      kFLEXSPI_PortB1
#define NAND_EXAMPLE_FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkLoopbackInternally

#define NAND_CMD_LUT_SEQ_IDX_READ_NORMAL        7
#define NAND_CMD_LUT_SEQ_IDX_PAGE_READ          13
#define NAND_CMD_LUT_SEQ_IDX_READ_FAST_QUAD     0
#define NAND_CMD_LUT_SEQ_IDX_READBBMLUT         1
#define NAND_CMD_LUT_SEQ_IDX_WRITEENABLE        2
#define NAND_CMD_LUT_SEQ_IDX_ERASESECTOR        3
#define NAND_CMD_LUT_SEQ_IDX_PAGEPROGRAM_LOAD   6
#define NAND_CMD_LUT_SEQ_IDX_PAGEPROGRAM_EXE    4
#define NAND_CMD_LUT_SEQ_IDX_READID             8
#define NAND_CMD_LUT_SEQ_IDX_WRITESTATUSREG     9
#define NAND_CMD_LUT_SEQ_IDX_ENTERQPI           10
#define NAND_CMD_LUT_SEQ_IDX_EXITQPI            11
#define NAND_CMD_LUT_SEQ_IDX_READSTATUSREG      12
#define NAND_CMD_LUT_SEQ_IDX_ERASECHIP          5

#define CUSTOM_LUT_LENGTH        60
#define FLASH_QUAD_ENABLE        0x40
#define FLASH_BUSY_STATUS_POL    1
#define FLASH_BUSY_STATUS_OFFSET 0
#define CACHE_MAINTAIN           1

/*${macro:end}*/

/*******************************************************************************
 * Variables
 ******************************************************************************/
/*${variable:start}*/
#if (defined CACHE_MAINTAIN) && (CACHE_MAINTAIN == 1)
typedef struct _flexspi_cache_status
{
    volatile bool DCacheEnableFlag;
    volatile bool ICacheEnableFlag;
} flexspi_cache_status_t;
#endif
/*${variable:end}*/

/*******************************************************************************
 * Prototypes
 ******************************************************************************/
/*${prototype:start}*/
void BOARD_InitHardware(void);

static inline void flexspi_clock_init(void)
{
    const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};

    CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 24);   /* Set PLL3 PFD0 clock 360MHZ. */
    CLOCK_SetMux(kCLOCK_FlexspiMux, 0); /* Choose PLL3 PFD0 clock as flexspi source clock. */
    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);   /* flexspi clock 120M. */
}
/*${prototype:end}*/

#endif /* _APP_H_ */
